As desired wafer level scaling continues to occur at a pace faster than improvements in lithographic equipment can be delivered, lithographers will have to implement patterning solutions based on decreasing image resolution. The lithographic process that transfers a pattern from a mask to a wafer includes process nonlinearities and it is the lithographer's responsibility to create a robust mask-to-wafer lithographic process in which the nonlinearities are stable over time. One technique that is used to help ease the burden placed on the lithographer is to restrict the variety of patterns that can be printed on any given level (Liebmann et al., High-Performance Circuit Design for the RET-enabled 65 nm Technology Node, in Design and Process Integration for Microelectronic Manufacturing II, Proc. of SPIE, Vol. 5379, 2004, pp. 20-29). This allows the lithography process to be more easily optimized. Unfortunately, this use of restricted design rules just transfers the burden from the lithographer to the designer, who now is left with the difficult task of redesigning layouts in a very restricted environment. Since it is very difficult for the lithographer to 1) predict what design geometries they may be asked to print and 2) know how well each geometry will print on the wafer, the lithographer will often attempt to impose severe restrictions on the designer. In this way, the lithographer can ensure that the relatively small variety of patterns will all print with sufficient process latitude. The drawback of this is that the designer is so severely restricted that it may no longer make sense to scale the design and the lithographer has often times disallowed geometries that could be printed without trouble. This problem is confounded by the fact that the designer and the lithographer often do not understand each others needs and don't share common terminology that would better facilitate the required communication.
It is the role of the optical proximity correction (OPC) engineer to try to resolve these disparities and find a compromise solution. The OPC engineer's role is to modify the design shapes prior to mask build in order to account for process nonlinearities. The lithographer's requirements are often communicated to the OPC engineer through a process model and a set of process requirements. Lithography simulation software can then be used by the OPC engineer to simulate the lithography process, giving the OPC engineer a very detailed understanding of the lithographic process. Although OPC engineers have all the tools they need to determine whether a geometry will cause problems in lithography, the design rules must still be restricted in order to keep designers from using these geometries.
In addition, the focus of OPC to date has been to accurately replicate the designed layout patterns on the wafer under nominal imaging conditions. As lithography is being pushed closer to fundamental resolution limits, it is becoming increasingly important to balance patterning accuracy at nominal conditions against patterning robustness over a range of process variations. Commonly referred to as process window optimization, the goal is to maximize the range of dose and defocus over which acceptable image tolerances can be maintained. Key to process window OPC (for example, see U.S. Pat. No. 6,578,290 to Ferguson et al., and Lugg et al., Adaptive OPC with a conformal target layout, Proc. SPIE Vol. 4691, p. 1091-1096, Optical Microlithography XV, July, 2002.) is an accurate and efficient means of communicating acceptable image tolerances from the designer to the lithographer. While it is theoretically conceivable to judge acceptable imaging by doing device and circuit simulations on the predicted patterning results (Balasinski et al., Impact of subwavelength CD tolerance on device performance, Proc. SPIE, Vol. 4692, p. 361-368, Design, Process Integration, and Characterization for Microelectronics, July 2002.), these techniques do not lend themselves to the high speed geometrical manipulations necessary for practical OPC or model-based process window analysis on large integrated circuit designs. It is therefore desirable to communicate to the lithographer the designer's intent and acceptable image tolerances geometrically while efficiently capturing complex inter-and intra-design level dependencies.
Currently, designers already convey many of their requirements to the OPC engineer through a set of design layers. Typically, each design layer contains a logical grouping of shapes; for example, of shapes that correspond roughly to a lithographic mask which is used to image and/or print a set of features on the wafer. For example, one layer may represent the shapes corresponding to the active areas, another layer of shapes corresponds to conductive lines, such as polysilicon gate conductor lines, while yet another layer corresponds to contact shapes, and so on. However, the term “layer” is not limited to a physical layer on the wafer, but may also refer to any logical grouping of shapes on a plane. Thus, a physical layer on the wafer or a particular mask design may correspond to shapes existing on multiple logical “layers.” Currently, these layers are processed independently and OPC is required to strictly replicate each of the layers in the final wafer printing. Although some inter-level checking is done to try to determine which areas of the design are more important than others, this checking is very limited and very rudimentary. Since the OPC engineer must replicate the design exactly as it is drawn, the additional information contained in the relationships between layers can never be used. However, if OPC engineers had the freedom to adjust the design without changing the functionality, they would have the ability to determine the optimal geometries for lithography. In this way, the designers' desired functionality can be achieved, while removing all conditions that will cause problems in the lithography process.
In view of the above, there is a need in the semiconductor industry to provide an improved method of designing lithographic masks that permits optimization of the mask layout and achieves maximal process windows without unduly restricting the rules of the circuit design.